Optical sensors for extreme low-level light conditions can convert single photons into a measurable electrical signal. Single-photon detectors, as these sensors are called, can be employed in vision systems with 3D imaging and range capability, for sensing at night or in caves, for low data rate intra- and inter-platform communications, and for molecular sensing in bio-analytical fluorescence imaging. One of the first technologies in the prior art capable of sensing single photons are photomultiplier tubes (PMT). Unfortunately, PMTs are bulky, easily damaged, expensive, susceptible to magnetic fields, and require high voltages for operation.
Another technology capable of converting single photons to a measurable electrical signal is avalanche photodiodes. An avalanche photodiode can be made to detect single photons when operated above its breakdown voltage in what is known as Geiger mode in which a single incident photon can trigger an “infinite” amount of photocurrent. Since any generated carrier, wanted or otherwise, can trigger an “infinite” amount of photocurrent, an avalanche photodiode that operates in Geiger mode should meet stringent dark current and noise requirements to operate above breakdown. A design of such an avalanche photodiode should guarantee that the pn junction that forms the multiplication region of the diode has the lowest breakdown voltage of any two abutting regions which in general will have doping levels that are different. Further, premature breakdown along any edges or corners of the primary junction that forms the multiplication region should be prevented. In the past, specialized fabrication steps were needed to meet these requirements, but in recent years, single-photon avalanche detectors (SPAD) made from avalanche photodiodes that operate in Geiger mode and manufactured using CMOS processes have been demonstrated.
The earliest approach to fabricating arrays of SPADs in CMOS used a custom process which integrated the SPADs with a companion CMOS timing chip using backside bridge bonding, as found in B. Aull, A. Loomis, D. Young, It Heinrichs, B. Felton, P. Daniels, and D. Landers, “Geiger mode avalanche photodiodes for three-dimensional imaging,” Lincoln Laboratory Journal, vol. 13, no. 2, pp. 335-345, 2002. The resulting arrays were limited in size to 32×32 pixels, and required significant post-processing to connect readout circuitry. In A. Rochas, M. Gosch, A. Serov, P. Besse, R. Popovic, T. Lasser, and R. Rigler, “First fully integrated 2-D array of single-photon detectors in standard CMOS technology,” IEEE Photonics Technology Letters, vol. 15, no. 7, pp. p963-965, July 2003 and M. Sergio and E. Charbon, “An Intra-chip electro-optical channel,” IEDM Technical Digest, pp. 819-822, December 2005, integrated SPADs have been demonstrated using high voltage CMOS processes. High voltage CMOS processes include special fabrication layers to allow the design of high voltage device structures necessary for the detector and the circuit elements in the pixel. Unfortunately, commercially available SPADs manufactured using high voltage CMOS processes suffer from reliability issues that limit the technology to feature sizes that are not competitive with low-voltage deep submicron and nano CMOS. This limits the ultimate density and usability of SPAD arrays manufactured using high voltage CMOS processes, to applications that do not require high quality or dense detector arrays. Fabrication steps that work to guarantee high breakdown voltages and eliminate latch-up often introduce leakage problems at crucial device interfaces. A Geiger mode CMOS SPAD manufactured using a non-high-voltage standard CMOS process employing a shallow-trench isolated structure is described in H. Finkelstein, M. J. Hsu, and S. C. Esener, “STI-bounded single-photon avalanche diode in a deep-submicrometer CMOS technology,” Electron Device Letters, vol. 27, no. 11, pp. 887-889, November 2006. This structure has a very high dark count, one of the basic figures of merit for SPADs. The high dark count is likely the result of using STI material to form a guard ring, which creates a poor material interface at a crucial location inside the device and fails to buffer the bottom corners of the multiplication region from undesirable edge effects. Note that the periphery area is much smaller than the bottom area of the device, and the undesirable effects on the bottom of the device will dominate and dictate its characteristics.
Accordingly, what would be desirable, but has not yet been provided, is a single photon avalanche photodiode pixel which can be formed into high density arrays, manufactured using standard foundry, non-customized, CMOS processes and exhibits few dark counts even at room temperature. It would also be desirable to manufacture such a pixel in a standard deep sub-micron and nano CMOS foundry using existing design rules so as to produce cost effective solutions for signal and information processing sub-systems that handle data from detector pixels and operate at speeds that are only achievable using CMOS circuits fabricated using deep submicron and nano CMOS technologies. What is also desirable is a mixed signal pixel that can be switched from single photon counting to a digital state holding pixel to accommodate high rate photon flux and effectively provide for infinite dynamic range sensing.